The Role of the Z80 PIO

The Z80 PIO (Parallel Input/Output) chip is a dedicated peripheral designed to relieve the Z80 CPU of the burden of managing complex, high-speed, general-purpose I/O. It provides two independent 8-bit ports (Port A and Port B), each configurable as input or output.

Advantage: The PIO handles handshaking and interrupt generation entirely in hardware, saving CPU cycles.

PIO Communication Ports

The PIO chip occupies four consecutive I/O port addresses on the Z80 bus, typically accessed via OUT and IN instructions:

Port Function Read/Write
A Data Port Transfers data (8 bits) to/from Port A. R/W
A Control Port Writes commands and control words for Port A. W
B Data Port Transfers data (8 bits) to/from Port B. R/W
B Control Port Writes commands and control words for Port B. W

Initialization: Setting the Mode

Before use, the Z80 must send a Control Word to the Control Port to define the PIO’s mode of operation.

Common Modes:

  1. Byte Output: All 8 bits are used for output.
  2. Byte Input: All 8 bits are used for input.
  3. Bit Control (Mode 3): Individual bits can be set as input or output.

Example: Setting Port A to Output Mode (Simplified)

PIO_PORT_A_CONTROL EQU 41H
PIO_PORT_A_DATA    EQU 40H

INIT_PIO:
    ; 1. Set Direction: Send control word 80H (Mode Select) + 0FH (Byte Output)
    LD   A, 80H        ; Start Mode Control
    OUT  (PIO_PORT_A_CONTROL), A
    
    LD   A, 0FH        ; 0FH = Set all 8 bits to Output
    OUT  (PIO_PORT_A_CONTROL), A
    RET

Interrupts and Handshaking

The PIO’s greatest benefit is interrupt management. The PIO can be configured to:

  1. Generate an Interrupt: When data is received on an input port (Port B), or when a transfer is complete on an output port (Port A).
  2. Vector Generation: In Z80 IM 2 mode, the PIO can supply the required Interrupt Vector Byte (Part 60) for its specific ISR.

This offloads the complex task of constantly polling I/O ports to the PIO chip’s hardware logic.