Advanced

The Complexity of Division While multiplication (Part 16) is complex, floating-point division is arguably the most difficult operation to implement in Z80 assembly. It combines the complexity of multi-byte arithmetic with the iterative processes of long division, applied across three components: Sign, Exponent, and Mantissa. The Formula (Conceptual): $$\text{Result}_{\text{Sign}} = \text{Operand}_A.\text{Sign} \text{ XOR } \text{Operand}B.\text{Sign}$$ $$\text{Result}{\text{Exponent}} = \text{Operand}_A.\text{Exponent} - \text{Operand}B.\text{Exponent}$$ $$\text{Result}{\text{Mantissa}} = \text{Operand}_A.\text{Mantissa} / \text{Operand}_B.\text{Mantissa}$$ Step 1: Sign and Exponent Calculation The sign of the result is determined by a simple XOR operation on the two input sign bits (Part 8). ...

The Cassette I/O Challenge The ZX Spectrum does not have a dedicated tape controller chip. All tape reading and writing is achieved through software routines that precisely control the timing of a single I/O line, which is one of the most demanding tasks for the Z80 CPU. The Principle: Data is encoded using Pulse Width Modulation (PWM), where the duration of the tone (the pulse width) determines whether the CPU sends a binary ‘0’ or a binary ‘1’. ...

The Challenge of the Spectrum Screen The ZX Spectrum screen memory is not linear. To save on hardware costs, the memory map was designed to simplify the display hardware’s access but complicate the CPU’s access. The Layout: The screen is divided into three major vertical bands, and within each band, the lines are interleaved. This means to find the address of the pixel at (X, Y), you must perform a complex, multi-step calculation. ...

The Challenge of Portability Throughout this series, we encountered system-specific hardware addresses: screen memory (4000H′), keyboard ports (FEH′), and sound chips (`AY-3-8910′). Code written for the ZX Spectrum will not run on an MSX or a CP/M machine without significant modification. Code Portability is the practice of writing code that minimizes these machine-specific differences, allowing the main logic to be compiled for multiple platforms. Method 1: Conditional Assembly The most fundamental technique is Conditional Assembly. The assembler is instructed to include or exclude specific blocks of code based on a platform constant defined at the beginning of the file. ...

The Application Layer’s Role The Application Layer (Layer 7) is the layer the user interacts with. Its job is to provide specific services and translate user input into the structures required by the Transport Layer (Part 66). Protocol 1: DNS (Domain Name Service) Users prefer typing names (google.com) rather than IP addresses. DNS is the protocol that translates these human-readable names into the 4-byte IP addresses required by the Network Layer. ...

The OSI Model and the Transport Layer The Transport Layer (Layer 4) is the crucial link between the application and the network. Its job is to ensure that data is delivered reliably (TCP) or quickly (UDP) between specific applications (identified by port numbers). Protocol 1: Connectionless (UDP Concepts) A connectionless protocol is fast but unreliable. Data is sent as individual datagrams without confirmation of receipt. This is ideal for time-sensitive data like video frames or game state updates. ...

The OSI Model and the Network Layer The Network Layer (Layer 3 of the OSI model) is responsible for logical addressing (e.g., IP addresses) and routing data packets between different networks. This is where your simple 4-byte addresses come into play. Goal: To wrap the Link Layer frame (Part 64) with a header that includes a Source Address and a Destination Address. Defining the Packet Structure Our simple network packet (often called a datagram) needs to sit inside the Link Layer frame and contain the necessary addressing information. ...

The OSI Model and the Link Layer Networking is organized into layers. The Link Layer (Layer 2 of the OSI model) is the lowest level of communication, responsible for sending and receiving frames (raw data packets) between two connected devices (e.g., two computers on a local network). Goal: To wrap user data with a small header and footer so the receiver knows where the packet begins, where it ends, and whether it’s valid. ...

The Role of the Z80 SIO The Z80 SIO (Serial Input/Output) chip is a sophisticated peripheral that acts as a dual-channel UART (Universal Asynchronous Receiver/Transmitter). It handles all the complex timing, start/stop bit generation, and error checking for serial communication entirely in hardware. Advantage: The SIO makes robust serial communication (like RS-232, modem, or network) fast and reliable, saving the Z80 CPU thousands of cycles compared to software bit-banging (Part 40). ...

The Role of the Z80 CTC The Z80 CTC (Counter/Timer Circuit) is a dedicated peripheral chip that provides four independent channels (Channel 0 to 3), each capable of acting as a counter or a timer. This chip is crucial for relieving the Z80 CPU of the burden of running software timing loops (Part 15). Advantage: The CTC allows for precise, hardware-based timing that operates in the background, freeing the CPU to run main program logic. ...