Assembly

Introduction to the Spectrum’s Memory Map The ZX Spectrum is a 48KB machine with a simple, fixed memory map. Understanding this map is crucial because the Z80 must interact with the screen and system variables at hardcoded addresses. The 64KB address space is divided into four main 16KB blocks: Address Range Size (KB) Content Usage 0000H - 3FFFH 16 KB System ROM Holds the BASIC interpreter and operating system kernel. 4000H - 7FFFH 16 KB Low RAM Holds the Display File (Screen + Attributes) and user data. 8000H - BFFFH 16 KB High RAM 1 General purpose user program space. C000H - FFFFH 16 KB High RAM 2 Used for user programs and the CPU Stack (grows downwards). The Display File (Screen Memory) The most important fixed addresses are those related to the screen, which resides in the low RAM area. ...

The Synthesis: Combining All 68 Lessons This final project demonstrates how to structure and link together all the advanced modules developed in this series (Interrupts, Graphics, I/O, and Logic) to create a working, real-time application. The Engine’s Goal: Display a sprite that moves smoothly in response to keyboard input, accelerates due to gravity, and stops when hitting a floor tile. Engine Initialization (The Setup Phase) This phase runs only once, at boot, and relies heavily on your OS and peripheral posts (Parts 52, 62). ...

The Challenge of Portability Throughout this series, we encountered system-specific hardware addresses: screen memory (4000H′), keyboard ports (FEH′), and sound chips (`AY-3-8910′). Code written for the ZX Spectrum will not run on an MSX or a CP/M machine without significant modification. Code Portability is the practice of writing code that minimizes these machine-specific differences, allowing the main logic to be compiled for multiple platforms. Method 1: Conditional Assembly The most fundamental technique is Conditional Assembly. The assembler is instructed to include or exclude specific blocks of code based on a platform constant defined at the beginning of the file. ...

The Application Layer’s Role The Application Layer (Layer 7) is the layer the user interacts with. Its job is to provide specific services and translate user input into the structures required by the Transport Layer (Part 66). Protocol 1: DNS (Domain Name Service) Users prefer typing names (google.com) rather than IP addresses. DNS is the protocol that translates these human-readable names into the 4-byte IP addresses required by the Network Layer. ...

The OSI Model and the Transport Layer The Transport Layer (Layer 4) is the crucial link between the application and the network. Its job is to ensure that data is delivered reliably (TCP) or quickly (UDP) between specific applications (identified by port numbers). Protocol 1: Connectionless (UDP Concepts) A connectionless protocol is fast but unreliable. Data is sent as individual datagrams without confirmation of receipt. This is ideal for time-sensitive data like video frames or game state updates. ...

The OSI Model and the Network Layer The Network Layer (Layer 3 of the OSI model) is responsible for logical addressing (e.g., IP addresses) and routing data packets between different networks. This is where your simple 4-byte addresses come into play. Goal: To wrap the Link Layer frame (Part 64) with a header that includes a Source Address and a Destination Address. Defining the Packet Structure Our simple network packet (often called a datagram) needs to sit inside the Link Layer frame and contain the necessary addressing information. ...

The OSI Model and the Link Layer Networking is organized into layers. The Link Layer (Layer 2 of the OSI model) is the lowest level of communication, responsible for sending and receiving frames (raw data packets) between two connected devices (e.g., two computers on a local network). Goal: To wrap user data with a small header and footer so the receiver knows where the packet begins, where it ends, and whether it’s valid. ...

The Role of the Z80 SIO The Z80 SIO (Serial Input/Output) chip is a sophisticated peripheral that acts as a dual-channel UART (Universal Asynchronous Receiver/Transmitter). It handles all the complex timing, start/stop bit generation, and error checking for serial communication entirely in hardware. Advantage: The SIO makes robust serial communication (like RS-232, modem, or network) fast and reliable, saving the Z80 CPU thousands of cycles compared to software bit-banging (Part 40). ...

The Role of the Z80 CTC The Z80 CTC (Counter/Timer Circuit) is a dedicated peripheral chip that provides four independent channels (Channel 0 to 3), each capable of acting as a counter or a timer. This chip is crucial for relieving the Z80 CPU of the burden of running software timing loops (Part 15). Advantage: The CTC allows for precise, hardware-based timing that operates in the background, freeing the CPU to run main program logic. ...

The Role of the Z80 PIO The Z80 PIO (Parallel Input/Output) chip is a dedicated peripheral designed to relieve the Z80 CPU of the burden of managing complex, high-speed, general-purpose I/O. It provides two independent 8-bit ports (Port A and Port B), each configurable as input or output. Advantage: The PIO handles handshaking and interrupt generation entirely in hardware, saving CPU cycles. PIO Communication Ports The PIO chip occupies four consecutive I/O port addresses on the Z80 bus, typically accessed via OUT and IN instructions: ...